Frame buffered displays incorporate memory to store image data so that they can continue to refresh displayed image data without requiring an external data source. Such displays typically have two image data sources, one external to the display, such as video data supplied by an operating system executing on an external processor system, and the other supplied internally by a display controller or other logic. Because it has an internal image data source, a frame buffered display may permit selective gating or disabling of the external data source to save power. When the internally stored image data needs to be updated the external data source may be re-enabled to provide fresh image data to the display.
At the time that the external data source is re-enabled the internal data source and the external data source are likely to be out of synchronization. Standard display data sources or streams convey image data accompanied by two strobe signals: a vertical synchronization (Vsync) signal and a horizontal synchronization (Hsync) signal. The Vsync signal typically indicates when the display hardware should initiate or return to scanning the display data starting from the left-upper-most pixel of the display, while the Hsync signal typically indicates when the display hardware should begin scanning from the left-most pixel of each row of display pixels. When the two data sources are not synchronized the user may experience flickering or other display artifacts when the external data source is re-enabled because a significant interval or offset may exist between the Vsync signals of the two data sources.